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a
Preliminary Technical Data
FEATURES
Very low offset voltage: 10uV max over temperature Very low input offset voltage drift: 50nV/C max High CMRR: 96dB Digitally programmable gain (span) and output offset voltage Open and short wire fault detection Low pass filtering Externally programmable output clamp voltage for driving low-voltage ADCs Very wide input and output ranges Single supply operation from 2.7V to 5.5V supplies
Zero-Drift, Single-Supply, Sensor Signal Amplifier with Digitally Programmable Gain and Offset
AD8555
supply voltage variations. Output offset voltage can be adjusted with a resolution of better than 0.4% of the difference between VDD and VSS. A lockout trim after gain and offset adjustment further assures field reliability. AD8555AR is fully specified over the extended industrial (automotive) temperature range from -40C to +125C. Operating from single-supply voltages from 2.7V to 5.5V, the AD8555 is offered in the narrow 8-lead SOIC package and the 4 x 4mm 16-lead LFCSP.
8-Lead SOIC (R-8 Suffix)
APPLICATIONS
Brake pressure sensing Manifold pressure sensing Leak-down pressure detection Fuel pressure sensing Balanced bridge sensors Precision current sensing PRODUCT OVERVIEW
VDD FILT/DIGOUT DIGIN VNEG
1
AD8555
5
VSS VOUT VCLAMP VPOS
AD8555 is a zero-drift bridge sensor signal amplifier with digitally programmable gain and output offset. Designed to easily and accurately convert variable pressure sensor and strain bridge outputs to a well-defined output voltage range, AD8555 will also accurately amplify many other differential or single ended sensor outputs. AD8555 utilizes ADI's patented low noise auto-zero and DigiTrim(R) technologies to create an incredibly accurate and flexible signal processing solution in a very compact footprint. In addition to extremely low input offset voltage and input offset voltage drift and very high DC and AC CMRR, the AD8555 also includes a pull-up current source at each analog input to allow open wire and shorted wire fault detection, and a low-pass filter function implemented via a single low-cost external capacitor. Output clamping set via an external reference voltage allows the AD8555 to drive lower voltage ADCs safely and accurately. Gain is digitally programmable in a wide range from 70 to 1280 through a serial data interface. Gain adjustment can be fully simulated in-circuit and then permanently programmed with proven and reliable poly-fuse technology. Output offset voltage is also digitally programmable and is ratiometric to the supply voltage. When used in conjunction with an ADC referenced to the same supply, the system accuracy becomes immune to normal
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. All sales made pursuant to Analog Devices terms and conditions
16-Lead LFCSP (CP-16 Suffix)
AVDD
DVDD
16 15 14 13 NC 1 12 VOUT FILT/DIGOUT NC DIGIN 2 3 4 5 NC 6 VNEG 7 NC 8 VPOS AD8555 11 NC 10 VCLAMP 9 NC
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. World Wide Web Site: http://www.analog.com Tel: 617/329-4700 (c) Analog Devices, Inc., 2003 Fax: 617/326-8703
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DVSS
AVSS
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Preliminary Technical Data
ELECTRICAL SPECIFICATIONS
(@ VDD=+5.0V, VSS=0.0V VCM = +2.5V, VO=+2.5V, -40C
AD8555
Min Typ 3 18 10 1 0.9 70 96 32 50 20 1 1 5 9.6 1.8 0.6 100 16 700 1.1 5 5 8 3.6 Max 10 28 30 Units V nA nA pA nA nA nA V dB dB nV/Hz ppm ppm % ppm/C % mV ppm/C k ppm/C V V k mA MHz MHz
TA +125C unless otherwise specified.)
Parameter SYSTEM PERFORMANCE Input Offset Voltage Input Bias Current @ VPOS, VNEG Input Bias Current @VCLAMP Input Offset Current @ VPOS, VNEG Input Voltage Range @ VPOS, VNEG Common-Mode Rejection Ratio Input Referred Noise Ratiometricity Linearity Differential Gain Accuracy Differential Gain Temperature Coeff. DAC Accuracy DAC Offset DAC Temperature Coefficient RF RF Temperature Coefficient VCLAMP Input Range VD1 RP POWER SUPPLY Supply Current DYNAMIC PERFORMANCE Gain Bandwidth Product AMPLIFIER PERFORMANCE Amplifiers A1, A2, A3 INPUT CHARACTERISTICS Offset Voltage Offset Voltage Drift Input Bias Current Input Offset Current Input Voltage Range DYNAMIC PERFORMANCE Gain Bandwidth Product Amplifiers A1, A2 Amplifier A3 NOISE PERFORMANCE Voltage Noise Density
Symbol VOS IB
Conditions
TA = 25C TA = 25C
8
IOS
TA = 25C
CMRR
VCM = 0V to 3.9V, AV=70 VCM = 0V to 3.9V, AV=1280 TA = 25C
3 20 3 50 200 22.4 5 1.5
ISY GBP
VO = 2.5V 1st gain stage, TA = 25C 2nd gain stage, TA = 25C 2 8
4
VOS/T TA = 25C TA = 25C 0.5
3 0.01 30 50
10 0.05 100 200 3.9
V V/C pA pA V
GBP
TA = 25C TA = 25C f = 1kHz, TA = 25C
2 8 25
MHz MHz nV/Hz
en
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Preliminary Technical Data
Parameter DIGITAL INTERFACE INPUT CHARACTERISTICS DIGIN pulse width to load 0 DIGIN pulse width to load 1 time between pulses at DIGIN DIGIN low DIGIN high DIGOUT logic 0 DIGOUT logic 1 Symbol Conditions Min Typ Max tw0 tw1 tws TA = 25C TA = 25C TA = 25C TA = 25C TA = 25C TA = 25C TA = 25C 0.05 50 10 0 4 0 4 10
AD8555
Units s s s V V V V
1 5 1 5
ABSOLUTE MAXIMUM RATINGS Supply Voltage ..........................................................................+6V Input Voltage ........................................ VSS -0.3V to VDD + 0.3V Differential Input Voltage1 .....................................................5.0V Output Short-Circuit Duration to VSS or VDD............Indefinite Storage Temperature Range..........................-65C to +150C Operating Temperature Range........................40C to +125C Junction Temperature Range.........................-65C to +150C Lead Temperature Range (Soldering, 10 sec)................+300C
2
ORDERING GUIDE Model AD8555AR AD8555ACP Temperature Range -40C to +125C -40C to +125C Package Description 8-Lead SOIC 16-Lead LFCSP Package Option SO-8 CP-16
PIN FUNCTION DESCRIPTIONS SOIC / LFCSP Pin 1 / Pins 15, 16 Pin 2 / Pin 2 Name Function VDD / DVDD,AVDD Positive supply voltage FILT/DIGOUT Unbuffered amplifier output in series with a resistor RF. Adding a capacitor between FILT and VDD or VSS will implement a low-pass filtering function. In read mode, this pin functions as a digital output DIGIN Digital input VNEG Negative amplifier input (inverting input) VPOS Positive amplifier input (non-inverting input) VCLAMP Set clamp voltage at output VOUT Buffered amplifier output -buffered version of the signal at the FILT/DIGOUT pin. In read mode, VOUT is a buffered digital output. VSS / DVSS, AVSS Negative supply voltage
Package Type 8-Lead SOIC (R) 16-Lead LFCSP (CP) NOTES
JA
JC 43 31.5
Units C/W C/W
158 44
1 Differential input voltage is limited to 5.0 volts or the supply voltage, whichever is less. 2 JA is specified for the worst case conditions, i.e. JAis specified for device soldered in circuit board for SOIC and TSSOP packages.
Pin 3 / Pin 4 Pin 4 / Pin 6 Pin 5 / Pin 8 Pin 6 / Pin 10 Pin 7 / Pin 12
Pin 8 / Pins 13, 14
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Preliminary Technical Data
Theory of Operation
AD8555 Functional Schematic
VDD VDD VNEG
R4 A1 P3 VCLAMP R6
AD8555
A5 VSS
R1
VSS P1 R3 P2 VDD RF A3
VDD
VOUT
A4 VDD
R2
VSS R5 P4 VDD VDAC R7
FILT/ DIGOUT
VSS
VPOS
A2 VSS
DAC
VSS
A1, A2, R1, R2, R3, P1 and P2 form the first gain stage of the differential amplifier. A1 and A2 are auto-zeroed op-amps to minimize input offset errors. P1 and P2 are digital potentiometers, guaranteed to be monotonic. Programming of P1 and P2 allow the first stage gain to be varied from 4.0 to 6.4 with 7-bit resolution (see Table 1 and equation (3)), giving a fine gain adjustment resolution of 0.37%. R1, R2, R3, P1 and P2 each have a similar temperature coefficient, so the first stage gain temperature coefficient is lower than 200ppm/C. A3, R4, R5, R6, R7, P3 and P4 form the second gain stage of the differential amplifier. A3 is also an auto-zeroed op-amp to minimize input offset errors. P3 and P4 are digital potentiometers, allowing the second stage gain to be varied from 17.5 to 200 in 8 steps (see Table 2); they allow the gain to be varied over a wide range. R4, R5, R6, R7, P3 and P4 each have a similar temperature coefficient, so the second stage gain temperature coefficient is lower than 200ppm/C. RF together with an external capacitor connected between FILT/DIGOUT and VSS or VDD form a low pass filter. The filtered signal is buffered by A4 to give a low impedance output at VOUT. RF is nominally 16k, allowing a 1kHz low pass filter to be implemented by connecting a 10nF external capacitor between FILT/DIGOUT and VSS or between FILT/DIGOUT and VDD. If low-pass filtering is not needed then the FILT/DIGOUT pin must be left floating. A5 implements a voltage buffer which provides the positive supply to the amplifier output buffer A4. Its function is to limit VOUT to a maximum value, useful for driving analog-to-digital converters operating on supply voltages lower than VDD. The input to A5, VCLAMP, has a very high input resistance. It should be connected to a known voltage and not left floating. However, the high input impedance allows the clamp voltage to be set using high impedance source, e.g. a potential divider. If the maximum value of VOUT does not need to be limited, VCLAMP should be connected to VDD.
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Preliminary Technical Data
AD8555
A4 implements a rail-to-rail input and output unity-gain voltage buffer. The output stage of A4 is supplied from a buffered version of VCLAMP instead of VDD, allowing the positive swing to be limited. The maximum output current is limited between 5mA to 10mA. An 8-bit digital-to-analog converter (DAC) is used to generate a variable offset for the amplifier output. This DAC is guaranteed to be monotonic. To preserve the ratiometric nature of the input signal, the DAC references are driven from VSS and VDD, and the DAC output can swing from VSS (code 0) to VDD (code 255). The 8-bit resolution is equivalent to 0.39% of the difference between VDD and VSS (e.g. 19.5mV with a 5V supply). The DAC output voltage (VDAC) is given approximately by equation (1) below:
code + 0.5 VDAC (VDD - VSS ) + VSS 256
The temperature coefficient of VDAC is lower than 200ppm/C. The amplifier output voltage (VOUT) is given by equation (2) below:
(1)
VOUT = GAIN (VPOS - VNEG ) + VDAC
(2)
where GAIN is the product of the first and second stage gains.
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Preliminary Technical Data
Gain values
Table 1: First Stage Gain vs. Gain Code First Stage Gain Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 First Stage Gain 4.000 4.015 4.030 4.045 4.060 4.075 4.090 4.105 4.120 4.135 4.151 4.166 4.182 4.197 4.213 4.228 4.244 4.260 4.276 4.291 4.307 4.323 4.339 4.355 4.372 4.388 4.404 4.420 4.437 4.453 4.470 4.486 First Stage Gain Code 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 First Stage Gain 4.503 4.520 4.536 4.553 4.570 4.587 4.604 4.621 4.638 4.655 4.673 4.690 4.707 4.725 4.742 4.760 4.778 4.795 4.813 4.831 4.849 4.867 4.885 4.903 4.921 4.939 4.958 4.976 4.995 5.013 5.032 5.050 First Stage Gain Code 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95
code
AD8555
First Stage Gain 5.069 5.088 5.107 5.126 5.145 5.164 5.183 5.202 5.221 5.241 5.260 5.280 5.299 5.319 5.339 5.358 5.378 5.398 5.418 5.438 5.458 5.479 5.499 5.519 5.540 5.560 5.581 5.602 5.622 5.643 5.664 5.685
First Stage Gain Code 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127
First Stage Gain 5.706 5.727 5.749 5.770 5.791 5.813 5.834 5.856 5.878 5.900 5.921 5.943 5.965 5.988 6.010 6.032 6.054 6.077 6.099 6.122 6.145 6.167 6.190 6.213 6.236 6.259 6.283 6.306 6.329 6.353 6.376 6.400
6.4 127 GAIN1 4 * 4
(3)
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Preliminary Technical Data
Table 2: Second Stage Gain and Gain Ranges vs. Gain Code Second Stage Gain Code 0 1 2 3 4 5 6 7 Second Stage Gain 17.5 25 35 50 70 100 140 200 Minimum Combined Gain 70 100 140 200 280 400 560 800
AD8555
Maximum Combined Gain 112 160 224 320 448 640 896 1280
Open Wire Fault Detection
The inputs to A1 and A2, VNEG and VPOS, each have a comparator to detect whether VNEG or VPOS exceed a threshold voltage, nominally VDD-1.1V. If (VNEG > VDD-1.1V) OR (VPOS > VDD-1.1V), then VOUT is clamped to VSS. The output current limit circuit is disabled in this mode, but the maximum sink current is approximately 50mA when VDD=5V. The inputs to A1 and A2, VNEG and VPOS, are also pulled up to VDD by currents IP1 and IP2. These are nominally 18nA each, and matched to within 5nA. If the inputs to A1 or A2 are accidentally left floating (e.g. an open wire fault), then IP1 and IP2 will pull them to VDD, which would cause VOUT to swing to VSS, allowing this fault to be detected. It is not possible to disable IP1 and IP2, nor the clamping of VOUT to VSS when VNEG or VPOS approach VDD.
Shorted Wire Fault Detection
The AD8555 provides fault detection, in the case where VPOS, VNEG, and VCLAMP shorts to VDD and VSS. Figure 1 shows the voltage regions at VPOS, VNEG, and VCLAMP which trigger an error condition. When an error condition occurs, the VOUT pin is shorted to VSS. Table 3 lists the voltage levels shown in Figure 1. Figure 1: Voltage Regions at VPOS, VNEG, and VCLAMP, Which Trigger a Fault Condition
VPOS
VDD
VNEG
VDD
VCLAMP
VDD VINH
ERROR
VINH
ERROR NORMAL
NORMAL
NORMAL
VCLL
ERROR
VINL VSS
ERROR
VINL VSS
ERROR
VSS
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Preliminary Technical Data
Table 3: Definition of VINL, VINH and VCLL Voltage VINH VINL VCLL Minimum Value VDD - 1.3V 0.05 * VINH VSS + 1.0V Maximum Value VDD - 0.7V 0.15 * VINH VSS + 1.7V Purpose Short to VDD Fault Detection Short to VSS Fault Detection Short to VSS Fault Detection
AD8555
Floating VPOS, VNEG, or VCLAMP fault detection
A floating fault condition at the VPOS, VNEG, or VCLAMP pins is detected by using a low current to pull a floating input into an error voltage range defined in the previous section. In this way, the VOUT pin is shorted to VSS when a floating input is detected. Table 4 lists the currents used. Table 4: Floating Fault Detection at VPOS, VNEG, and VCLAMP Pin VPOS VNEG VCLAMP Current 12nA to 24nA pull-up 12nA to 24nA pull-up 0.3A to 2A pull-down Goal of Current Pull VPOS above VINH Pull VNEG above VINH Pull VCLAMP below VCLL
Device Programming
Digital Interface
The digital interface allows the first stage gain, second stage gain, and output offset to be adjusted and allows desired values for these parameters to be permanently stored by selectively blowing polysilicon fuses. To minimize pin count and board space, a single-wire digital interface is used. The digital input pin, DIGIN, has hysteresis to minimize the possibility of inadvertent triggering with slow signals. It also has a pull-down current sink to allow it to be left floating when programming is not being performed. The pull-down insures inactive status of the digital input by forcing a DC low voltage on DIGIN. A short pulse at DIGIN from low to high and back to low again (e.g. between 50ns and 10s long) loads a 0 into a shift register. A long pulse at DIGIN (e.g. 50s or longer) loads a 1 into the shift register. The time between pulses should be at least 10s. Assuming VSS=0V, voltages at DIGIN between VSS and 0.2*VDD are recognized as a low, and voltages at DIGIN between 0.8*VDD and VDD are recognized as a high. A timing diagram example showing the waveform for entering code 010011 into the shift register is shown in Figure 2. Figure 2: Timing diagram for code 010011
tw0 tws
tw1
tws tw0 tws tw0 tws
tw1
tws
tw1
waveform
code
0
1
0
0
1
1
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Preliminary Technical Data
Table 5: Timing Specifications Timing Parameter tw0 tw1 tws Description pulse width for loading 0 into shift register pulse width for loading 1 into shift register width between pulses
AD8555
Specification between 50ns and 10s >= 50s >= 10s
A 38-bit serial word is used, divided into 6 fields. Assuming each bit can be loaded in 60s, the 38-bit serial word to be transferred in 2.3ms. Table 6 summarizes the word format.
Table 6: 38-bit serial word format field 0 field 1 bits 0 to 11 bits 12 to 13 12-bit start of packet "1000 0000 0001" 2-bit function 00: change sense current 01: simulate parameter value 10: program parameter value 11: read parameter value 2-bit parameter 00: second stage gain code 01: first stage gain code 10: output offset code 11: other functions 2-bit dummy "10" 8-bit value parameter 00 (second stage gain code):3 LSBs used parameter 01 (first stage gain code): 7 LSBs used parameter 10 (output offset code): all 8 bits used parameter 11 (other functions): bit 0 (LSB): master fuse bit 1: fuse for production test at Analog Devices 12-bit end of packet "0111 1111 1110"
field 2
bits 14 to 15
field 3 field 4
bits 16 to 17 bits 18 to 25
field 5
bits 26 to 37
Fields 0 and 5 are the "start of packet" and "end of packet" fields respectively. Matching the "start of packet" field with "1000 0000 0001" and the "end of packet" field with "0111 1111 1110" ensure that the serial word is valid and enables decoding of the other fields. Field 3 breaks up the data and ensures that no data combination can inadvertently trigger the "start of packet" and "end of packet" fields. Field 0 should be written first and field 5 written last. Within each field, the MSB must be written first and the LSB written last. The shift register features power-on-reset to minimize the risk of inadvertent programming; power-on-reset occurs when VDD is between 0.7V and 2.2V.
Initial State
Initially, all the polysilicon fuses will be intact. Each parameter will have the value 0 assigned. See Table 7 below.
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Preliminary Technical Data
Table 7: Initial state before programming Second Stage Gain Code = 0 First Stage Gain Code = 0 Output Offset Code = 0 Master Fuse = 0 Second Stage Gain = 17.5 First Stage Gain = 4.0 Output Offset = VSS Master Fuse Not Blown
AD8555
When power is applied to a device, parameter values are taken either from internal registers if the master fuse is not blown, or from the polysilicon fuses if the master fuse is blown. Programmed values have no effect until the master fuse is blown. The internal registers feature power-on-reset so that unprogrammed devices enter a known state after power-up; power-on-reset occurs when VDD is between 0.7V and 2.2V.
Simulation Mode
The simulation mode allows any parameter to be changed temporarily. These changes are retained until the simulated value is reprogrammed, the power is removed or until the master fuse is blown. Parameters are simulated by setting field 1 to 01, selecting the desired parameter in field 2, and the desired value for the parameter in field 4. Note that a value of 11 for field 2 is ignored during the simulation mode. Examples of temporary settings are given below. Set the second stage gain code (parameter 00) to 011 and hence the second stage gain to 50: 1000 0000 0001 01 00 10 0000 0011 0111 1111 1110 Set the first stage gain code (parameter 01) to 000 1011 and hence the first stage gain to 4.166. 1000 0000 0001 01 01 10 0000 1011 0111 1111 1110 A first stage gain of 4.166 together with a second stage gain of 50 gives a total gain of 208.3. This gain will have a maximum tolerance of 3%. Set the output offset code (parameter 10) to 0100 0000 and hence the output offset to 1.260V when VDD=5V and VSS=0V. This output offset will have a maximum tolerance of 3%. 1000 0000 0001 01 10 10 0100 0000 0111 1111 1110
Programming Mode
Intact fuses give a bit value of 0. Bits with a desired value of 1 need to have the associated fuse blown. Since a relatively large current is needed to blow a fuse, only one fuse can be reliably blown at a time. Thus, a given parameter value may need several 38-bit words to allow reliable programming. A 5.5V supply is required when blowing fuses to minimize the ON resistance of the internal MOS switches which blow the fuse. The power supply must be able to deliver 250mA of current, and at least 0.1F of decoupling capacitance is needed across the power pins of the device. A minimum period of 1ms should be allowed for each fuse to blow. There is no need to measure the supply current during programming - the best way to verify correct programming is to use the read mode to read back the programmed values, and to re-measure the gain and offset to verify these values. Programmed fuses have no effect on the gain and output offset until the master fuse is blown; after blowing the master fuse, the gain and output offset are determined solely by the blown fuses and the simulation mode is permanently deactivated. Parameters are programmed by setting field 1 to 10, selecting the desired parameter in field 2, and a single bit with the value 1 in field 4. As an example, suppose the user wished to set the second stage gain permanently to 50. Parameter 00 needs to have the value 0000 0011 assigned. Two bits have the value 1, so two fuses need to be blown. Since only one fuse can be blown at a time, the code 1000 0000 0001 10 00 10 0000 0010 0111 1111 1110 can be used to blow one fuse. The MOS switch which blows the fuse closes when the complete packet is recognized, and opens when the start-of-packet, dummy, or end-of-packet fields are no longer valid. After 1ms, the second code
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Preliminary Technical Data
1000 0000 0001 10 00 10 0000 0001 0111 1111 1110 can be entered to blow the second fuse.
AD8555
To set the first stage gain permanently to a nominal value of 4.151, parameter 01 needs to have the value 000 1011 assigned. Three fuses need to be blown; the following codes can be used, with a 1ms delay after each code: 1000 0000 0001 10 01 10 0000 1000 0111 1111 1110 1000 0000 0001 10 01 10 0000 0010 0111 1111 1110 1000 0000 0001 10 01 10 0000 0001 0111 1111 1110 To set the output offset permanently to a nominal value of 1.260V when VDD=5V and VSS=0V, parameter 10 needs to have the value 0100 0000 assigned. One fuse needs to be blown, and the following code can be used: 1000 0000 0001 10 10 10 0100 0000 0111 1111 1110 Finally, to blow the master fuse to deactivate simulation mode and prevent further programming, the code 1000 0000 0001 10 11 10 0000 0001 0111 1111 1110 can be used. There are a total of 20 fuses. Since each fuse requires 1 ms to blow and each serial word can be loaded in 2.3 ms, the maximum time needed to program the fuses can be as low as 66 ms.
Parity Error Detection
A parity check is used to determine whether the programmed data of an AD8555 is valid, or whether data corruption has occurred in the non-volatile memory. Figure 3 shows the schematic implemented in the AD8555. Figure 3: Functional circuit of AD8555 parity check
VA0 to VA2 is the 3-bit control signal for the second stage gain, VB0 to VB6 is the 7-bit control signal for the first stage gain, and VC0 to VC7 is the 8-bit control signal for the output offset. PFUSE is the signal from the parity fuse, and MFUSE is the signal from the master fuse.
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AD8555
The function of the 2-input AND gate (cell and2) is to ignore the output of the parity circuit (signal par_sum) when the master fuse has not been blown. PARITY_ERROR is set to 0 when MFUSE = 0. In the simulation mode, for example, parity check is disabled. After the master fuse has been blown, i.e. after the AD8555 has been programmed, the output from the parity circuit (signal par_sum) is fed to PARITY_ERROR. When PARITY_ERROR is 0, the AD8555 behaves as a programmed amplifier. When PARITY_ERROR is 1, a parity error has been detected, and VOUT is connected to VSS. The 18-bit data signal (VA0 to VA2, VB0 to VB6, and VC0 to VC7) is fed to an 18-input exclusive-OR gate (cell eor18). The output of cell eor18 is the signal dat_sum. Dat_sum = 0 if there is an even number of 1's in the 18-bit word; dat_sum = 1 if there is an odd number of 1's in the 18-bit word. Examples are given in Table 8. Table 8: Examples of dat_sum Second Stage Gain Code 000 000 000 000 000 001 001 111 First Stage Gain Code 000 0000 000 0000 000 0000 000 0001 100 0001 000 0000 000 0001 111 1111 Output Offset Code 0000 0000 1000 0000 1000 0001 0000 0000 0000 0000 0000 0000 1000 0000 1111 1111 Number of Bits with 1 0 1 2 1 2 1 3 18 dat_sum 0 1 0 1 0 1 1 0
After the second stage gain, first stage gain, and output offset have been programmed, dat_sum should be computed and the parity bit should be set equal to dat_sum. If dat_sum is 0, the parity fuse should not be blown in order for the PFUSE signal to be 0. If dat_sum is 1, the parity fuse should be blown to set the PFUSE signal to 1. The code to blow the parity fuse is: 1000 0000 0001 10 11 10 0000 0100 0111 1111 1110 After the setting the parity bit, the master fuse can be blown to prevent further programming, using the code: 1000 0000 0001 10 11 10 0000 0001 0111 1111 1110 Signal par_sum is the output of the 2-input exclusive-OR gate (cell eor2). After the master fuse has been blown, PARITY_ERROR is set to par_sum. As mentioned earlier, the AD8555 behaves as a programmed amplifier when PARITY_ERROR = 0 (no parity error). On the other hand, VOUT is connected to VSS when a parity error has been detected (i.e. when PARITY_ERROR = 1).
Read Mode
The values stored by the polysilicon fuses can be sent to the FILT/DIGOUT pin to verify correct programming. Normally, the FILT/DIGOUT pin is connected only to the second gain stage output via RF. During read mode, however, the FILT/DIGOUT pin is also connected to the output of a shift register to allow the polysilicon fuse contents to be read. Since VOUT is a buffered version of FILT/DIGOUT, VOUT will also output a digital signal during read mode. Read mode is entered by setting field 1 to 11 and selecting the desired parameter in field 2; field 4 is ignored. The parameter value, stored in the polysilicon fuses, is loaded into an internal shift register, and the MSB of the shift register is connected to the FILT/DIGOUT pin. Pulses at DIGIN shift the shift register contents out to the FILT/DIGOUT pin, allowing the 8-bit parameter value to be read after seven additional pulses; shifting occurs on the falling edge of DIGIN. An eighth pulse at DIGIN disconnects FILT/DIGOUT from the shift register and terminates the read mode. If a parameter value is less than 8 bits long, the MSBs of the shift register are padded with 0s. For example, to read the second stage gain, the code 1000 0000 0001 11 00 10 0000 0000 0111 1111 1110 can be used. Since the second stage gain parameter value is only three bits long, the FILT/DIGOUT pin will have a value of 0 when this code is entered, and will remain 0 during four additional pulses at DIGIN. The fifth, sixth and seventh pulse at DIGIN
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Preliminary Technical Data
AD8555
will return the 3-bit value at FILT/DIGOUT, the seventh pulse returning the LSB. An eighth pulse at DIGIN terminates the read mode.
Sense Current
A sense current is sent across each polysilicon fuse to determine whether it has been blown or not. When the voltage across the fuse is less than approximately 1.5V, the fuse is considered not blown and logic 0 is output from the OTP cell. When the voltage across the fuse is greater than approximately 1.5V, the fuse is considered blown and logic 1 is output. When the AD8555 is manufactured, all fuses have a low resistance. When a sense current is sent through the fuse, a voltage less than 0.1V is developed across the fuse. This is much lower than 1.5V, so a logic 0 is output from the OTP cell. When a fuse is electrically blown, it should have a very high resistance. When the sense current is applied to the blown fuse, the voltage across the fuse should be larger than 1.5V, so logic 1 is output from the OTP cell. It is theoretically possible (though very unlikely) for a fuse to be incompletely blown during programming, assuming the required conditions are met. In this situation, the fuse could have a medium resistance (neither low nor high), and a voltage of approximately 1.5V could be developed across the fuse. Thus, the OTP cell could sometimes output a logic 0 or a logic 1, depending on temperature, supply voltage and other variables. To detect this undesirable situation, the sense current can be lowered by a factor of 4 using a special code. The voltage developed across the fuse would then change from 1.5V to 0.38V, and the output of the OTP would be a logic 0 instead of the logic 1 expected from a blown fuse. Correctly blown fuses would still output a logic 1. In this way, incorrectly blown fuses can be detected. Another special code would return the sense current to the normal (larger) value. The sense current cannot be permanently programmed to the low value. When the AD8555 is powered up, the sense current defaults to the high value. The code to use the low sense current is: 1000 0000 0001 00 00 10 XXXX XXX1 0111 1111 1110 The code to use the normal (high) sense current is: 1000 0000 0001 00 00 10 XXXX XXX0 0111 1111 1110
Suggested Programming Procedure
1. Set VDD and VSS to desired values in the application. Use simulation mode to test and determine desired codes for second stage gain, first stage gain, and output offset. The nominal values for these parameters are given by Tables 1 and 2, and Equations (1) and (2); the codes corresponding to these values can be used as a starting point. However, since actual parameter values for given codes will vary from device to device, some fine tuning will be necessary for the best possible accuracy. One way to choose these values is to set the output offset to an approximate value (e.g. code 128 for mid-supply) to allow the required gain to be determined. Then, set the second stage gain such that the minimum first stage gain (code 0) gives a lower gain than required, and the maximum first stage gain (code 127) gives a higher gain than required. After choosing the second stage gain, the first stage gain can be chosen to fine tune the total gain. Finally, the output offset can be adjusted to give the desired value. After determining the desired codes for second stage gain, first stage gain, and output offset, the device is ready for permanent programming. 2. Set VSS to 0V and VDD to 5.5V. Use program mode to permanently enter the desired codes for second stage gain, first stage gain, and output offset. Blow the master fuse to allow the AD8555 to read data from the fuses and to prevent further programming. Set VDD and VSS to desired values in the application. Use read mode with low sense current followed by high sense current to verify programmed codes. Measure gain and offset to verify correct functionality.
3. 4.
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Preliminary Technical Data
Suggested Algorithm to Determine Optimal Gain and Offset Codes
1. 2A. Determine desired gain, GA (e.g. using measurements).
AD8555
2B. 3A. 3B. 3C. 3D. 3E. 3F. 3G. 3H. 3I. 3J. 4A. 4B. 4C. 4D. 4E. 4F. 4G. 4H. 4I. 4J.
Use Table 2 to determine the second stage gain G2 such that (4.00*1.04) < (GA/G2) < (6.4/1.04). This ensures that the first and last codes for the first stage gain are not used, thereby allowing enough first stage gain codes within each second stage gain range to adjust for the 3% accuracy. Use simulation mode to set the second stage gain to G2. Set the output offset to allow the AD8555 gain to be measured (e.g. use code 128 to set it to mid-supply). Use Table 1 or Equation (3) to set the first stage gain code CG1 such that first stage gain is nominally GA/G2. Measure resulting gain GB. GB should be within 3% of GA. Calculate first stage gain error (in relative terms) EG1 = GB/GA - 1. Calculate error (in number of first stage gain codes) CEG1 = EG1/0.00370. Set first stage gain code to CG1 - CEG1. Measure gain GC. GC should be closer to GA than GB. Calculate error (in relative terms) EG2 = GC/GA - 1. Calculate error (in number of first stage gain codes) CEG2 = EG2/0.00370. Set first stage gain code to CG1 - CEG1 - CEG2. The resulting gain should be within one code of GA. Determine desired output offset OA (e.g. using measurements). Use equation (1) to set output offset code CO1 such that output offset is nominally OA. Measure output offset OB. OB should be within 3% of OA. Calculate error (in relative terms) EO1 = OB/OA - 1. Calculate error (in number of output offset codes) CEO1 = EO1/0.00392. Set output offset code to CO1 - CEO1. Measure output offset OC. OC should be closer to OA than OB. Calculate error (in relative terms) EO2 = OC/OA - 1. Calculate error (in number of output offset codes) CEO2 = EO2/0.00392. Set output offset code to CO1 - CEO1 - CEO2. The resulting offset should be within one code of OA.
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Preliminary Technical Data
AD8555
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